Current Program Status Register

The Linux/ARM embedded platform

Jason D. Bakos , in Embedded Systems, 2016

1.5.two Status register

ARM v6/v7 maintains a status register chosen the CPSR (current program status register) that holds iv status bits, negative (N), zero (Z), comport (C), and overflow (O). These bits can be used for conditional execution of subsequent instructions.

The $.25 are set up according to the most recently executed ALU educational activity that includes the special "south" suffix. For case, the " adds " instruction volition modify the status $.25 but the " add " instruction will not.

Near all ARM instructions can include an optional condition code that determines if the instruction will exist executed or skipped over. In other words, an instruction whose status code is evaluated to false volition not modify the land of the processor, such as writing a event annals to changing the PC.

For example, the ldreq instruction will but execute if the Z-flake in the CPSR is set up, which will be the case if the well-nigh recent computational education resulted in a result of zero.

For case, the sequence:

subs r2,r2,#1

streq r3, [r0]

…will decrement annals r2 and store r3 only if the new value of r2 is zero.

The compare (cmp) instruction can be used to set the status bits without any other side outcome.

For case:

cmp r2,r3

streq r4, [r0]

…will store register r4 merely if the contents of registers r2 and r3 are equal.

When combining the condition lawmaking and the "s" suffix, the status code comes first, for example,

addeqs r0,r0,r1

The complete list of provisional suffixes are shown in Tabular array 1.1.

Table 1.i. Status Codes

Suffix Flags Pregnant
eq z prepare Equal
ne z clear Not equal
hs c set Unsigned   >   =
lo c clear Unsigned <
mi n set Negative
pl n clear Positive or zero
vs v fix Overflow
vc v clear No overflow
hi c set and z clear Unsigned >
ls c articulate and z gear up Unsigned   <   =
ge n and five the same Signed   >   =
lt northward and v different Signed <
gt z clear, or north and v the same Signed >
le z fix, or due north and v unlike Signed   <   =

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ARM PROCESSOR FUNDAMENTALS

ANDREW Due north. SLOSS , ... CHRIS WRIGHT , in ARM Arrangement Developer's Guide, 2004

ii.2.1 PROCESSOR MODES

The processor style determines which registers are active and the access rights to the cpsr register itself. Each processor style is either privileged or nonprivileged: A privileged mode allows full read-write access to the cpsr. Conversely, a nonprivileged mode simply allows read access to the command field in the cpsr but withal allows read-write access to the condition flags.

At that place are vii processor modes in total: half-dozen privileged modes (abort, fast interrupt request, interrupt request, supervisor, system, and undefined) and one nonprivileged mode (user).

The processor enters abort fashion when there is a failed attempt to access memory. Fast interrupt request and interrupt asking modes correspond to the two interrupt levels available on the ARM processor. Supervisor mode is the mode that the processor is in afterwards reset and is generally the way that an operating system kernel operates in. Organisation style is a special version of user manner that allows full read-write access to the cpsr. Undefined mode is used when the processor encounters an didactics that is undefined or not supported past the implementation. User mode is used for programs and applications.

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Compages

Sarah L. Harris , David Money Harris , in Digital Pattern and Reckoner Architecture, 2016

Exception Treatment

Now that nosotros have defined execution modes, exception vectors, and banked registers, nosotros can define what occurs during an exception. Upon detecting an exception, the processor:

1.

Stores the CPSR into the banked SPSR

two.

Sets the execution manner and privilege level based on the type of exception

3.

Sets interrupt mask bits in the CPSR so that the exception handler will not be interrupted

4.

Stores the render address into the banked LR

5.

Branches to the exception vector table based on the type of exception

The processor and so executes the instruction in the exception vector table, typically a branch to the exception handler. The handler unremarkably pushes other registers onto its stack, takes intendance of the exception, and pops the registers back off the stack. The exception handler returns using the MOVS PC, LR educational activity, a special flavour of MOV that performs the following cleanup:

1.

Copies the banked SPSR to the CPSR to restore the status annals

2.

Copies the banked LR (perhaps adjusted for certain exceptions) to the PC to render to the program where the exception occurred

three.

Restores the execution mode and privilege level

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Porting Applications from the ARM7 to the Cortex-M3

Joseph Yiu , in The Definitive Guide to the ARM Cortex-M3 (Second Edition), 2010

eighteen.ii.2 Interrupts

The second target is the difference in the interrupt controller beingness used. Programme code to control the interrupt controller, such equally enabling or disabling interrupts, will demand to be changed. In addition, new lawmaking is required for setting upward interrupt priority levels and vector addresses for various interrupts.

The interrupt render method is also changed. This requires modification of interrupt render in assembler code or, if C language is used, information technology might exist necessary to brand adjustments on compile directives.

Enable and disable of interrupts, previously done past modifying Current Program Status register (CPSR), must be replaced by setting upward the Interrupt Mask annals. In add-on, in the ARM7TDMI, information technology is possible to reenable interrupt at the aforementioned time as interrupt render due to restore of CPSR from Saved Program Status register (SPSR). In the Cortex-M3, if interrupts are disabled during an interrupt handler by setting PRIMASK, the PRIMASK should be cleared manually before interrupt return. Otherwise, the interrupts will remain disabled.

In the Cortex-M3, some registers are automatically saved past the stacking and unstacking mechanisms. Therefore, some of the software stacking operations could be reduced or removed. All the same, in the case of the Fast Interrupt request (FIQ) handler, traditional ARM cores take split registers for FIQ (R8–R11). Those registers tin can exist used by the FIQ without the need to push them into the stack. Yet, in the Cortex-M3, these registers are not stacked automatically, so when an FIQ handler is ported to the Cortex-M3, either the registers existence used by the handler must be changed or a stacking step volition exist needed.

Code for nested interrupt handling can be removed. In the Cortex-M3, the NVIC has built-in nested interrupt treatment.

There are likewise differences in error handling. The Cortex-M3 provides diverse error status registers so that the cause of faults can exist located. In addition, new fault types are divers in the Cortex-M3 (due east.g., stacking and unstacking faults, retentiveness management faults, and hard faults). Therefore, mistake handlers will need to be rewritten.

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Instruction Sets

Marilyn Wolf , in Computers equally Components (Quaternary Edition), 2017

2.3.2 Data operations

Arithmetic and logical operations in C are performed in variables. Variables are implemented as retention locations. Therefore, to exist able to write instructions to perform C expressions and assignments, we must consider both arithmetic and logical instructions also equally instructions for reading and writing memory.

Fig. 2.eight shows a sample fragment of C code with data declarations and several assignment statements. The variables a, b, c, 10, y, and z all become data locations in memory. In most cases data are kept relatively separate from instructions in the program's retentivity image.

Figure 2.8. A C fragment with data operations.

ARM programming model

In the ARM processor, arithmetic and logical operations cannot be performed directly on memory locations. While some processors allow such operations to directly reference principal memory, ARM is a load-shop architecture—data operands must first be loaded into the CPU and so stored back to main retention to salve the results. Fig. 2.nine shows the registers in the basic ARM programming model. ARM has 16 general-purpose registers, r0 through r15. Except for r15, they are identical—any operation that tin can be done on one of them can be done on the others. The r15 register has the same capabilities as the other registers, but information technology is as well used equally the program counter. The program counter should of class not be overwritten for use in data operations. However, giving the PC the properties of a general-purpose register allows the program counter value to be used as an operand in computations, which can make certain programming tasks easier.

Figure 2.9. The basic ARM programming model.

The other of import basic annals in the programming model is the current program status register (CPSR). This register is set up automatically during every arithmetic, logical, or shifting functioning. The height four bits of the CPSR hold the following useful information most the results of that arithmetic/logical operation:

•

The negative (N) bit is gear up when the result is negative in two'southward-complement arithmetic.

•

The zero (Z) bit is set when every scrap of the upshot is zero.

•

The carry (C) bit is set when there is a carry out of the operation.

•

The overflow (V) bit is gear up when an arithmetic operation results in an overflow.

These bits tin can exist used to easily cheque the results of an arithmetics operation. Notwithstanding, if a chain of arithmetic or logical operations is performed and the intermediate states of the CPSR bits are important, they must be checked at each step because the next operation changes the CPSR values.

Example ii.1 illustrates the computation of CPSR bits.

Example 2.1 Status Bit Ciphering in the ARM

An ARM discussion is 32 bits. In C notation, a hexadecimal number starts with 0x, such as 0xffffffff, which is a 2'southward-complement representation of −ane in a 32-bit discussion.

Here are some sample calculations:

•

−one  + i  = 0: Written in 32-bit format, this becomes 0xffffffff   +   0x1   =   0x0, giving the CPSR value of NZCV   =   1001.

•

0  − i  =   −ane: 0x0   −   0x1   =   0xffffffff, with NZCV   =   1000.

•

two 31   − i  + one  =   −2 31 : 0x7fffffff   +   0x1   =   0x80000000, with NZCV   =   0101.

The basic class of a data pedagogy is simple:

      Add together r0,r1,r2

This educational activity sets register r0 to the sum of the values stored in r1 and r2. In improver to specifying registers as sources for operands, instructions may as well provide immediate operands, which encode a abiding value directly in the instruction. For example,

      ADD r0,r1,#two

      Sets r0 to r1 + 2.

The major data operations are summarized in Fig. 2.10. The arithmetic operations perform addition and subtraction; the with-carry versions include the current value of the bear bit in the computation. RSB performs a subtraction with the lodge of the two operands reversed, so that RSB r0,r1,r2 sets r0 to be r2   −   r1. The scrap-wise logical operations perform logical AND, OR, and XOR operations (the exclusive-or is called EOR). The BIC educational activity stands for bit clear: BIC r0,r1,r2 sets r0 to r1 and not r2. This didactics uses the second source operand as a mask: Where a bit in the mask is 1, the respective bit in the first source operand is cleared. The MUL instruction multiplies two values, but with some restrictions: No operand may be an immediate, and the ii source operands must be different registers. The MLA instruction performs a multiply-accumulate operation, particularly useful in matrix operations and signal processing. The didactics MLA   r0,r1,r2,r3 sets r0 to the value r1 × r2 + r3.

Figure 2.ten. ARM data instructions.

The shift operations are not dissever instructions—rather, shifts tin can be practical to arithmetic and logical instructions. The shift modifier is e'er applied to the 2d source operand. A left shift moves bits up toward the near-significant bits, while a right shift moves $.25 down to the least-pregnant bit in the word. The LSL and LSR modifiers perform left and correct logical shifts, filling the least-meaning bits of the operand with zeroes. The arithmetic shift left is equivalent to an LSL, only the ASR copies the sign flake—if the sign is 0, a 0 is copied, while if the sign is 1, a ane is copied. The rotate modifiers always rotate right, moving the $.25 that fall off the least-significant bit up to the almost-significant bit in the word. The RRX modifier performs a 33-flake rotate, with the CPSR'due south C bit beingness inserted above the sign bit of the give-and-take; this allows the carry bit to be included in the rotation.

The instructions in Fig. ii.11 are comparison operands—they do not modify general-purpose registers but only prepare the values of the NZCV bits of the CPSR register. The compare educational activity CMP r0, r1 computes r0   −   r1, sets the condition bits, and throws away the issue of the subtraction. CMN uses an add-on to set up the status bits. TST performs a scrap-wise AND on the operands, while TEQ performs an sectional-or.

Figure 2.11. ARM compare instructions.

Fig. ii.12 summarizes the ARM move instructions. The instruction MOV r0,r1 sets the value of r0 to the current value of r1. The MVN instruction complements the operand bits (ane'due south complement) during the move.

Figure 2.12. ARM move instructions.

Values are transferred betwixt registers and memory using the load-store instructions summarized in Fig. ii.13. LDRB and STRB load and store bytes rather than whole words, while LDRH and SDRH operate on half-words and LDRSH extends the sign bit on loading. An ARM address may be 32 bits long. The ARM load and shop instructions exercise not direct refer to chief retentiveness addresses, because a 32-bit address would not fit into an pedagogy that included an opcode and operands. Instead, the ARM uses register-indirect addressing. In annals-indirect addressing, the value stored in the register is used equally the address to be fetched from memory; the result of that fetch is the desired operand value. Thus, as illustrated in Fig. 2.xiv, if nosotros gear up r1  =   0x100, the didactics

Figure 2.13. ARM load-store instructions and pseudo-operations.

Figure two.fourteen. Annals-indirect addressing in the ARM.

      LDR r0,[r1]

sets r0 to the value of retention location 0x100. Similarly, STR   r0,   [r1] would store the contents of r0 in the retentiveness location whose address is given in r1. There are several possible variations:

      LDR r0,[r1, -r2]

loads r0 from the address given by r1 − r2, while

      LDR r0,[r1, #4]

loads r0 from the address r1   +   4.

This begs the question of how nosotros get an accost into a register—we need to exist able to set a register to an arbitrary 32-bit value. In the ARM, the standard fashion to gear up a annals to an address is by performing arithmetic on a register. 1 choice for the register to apply for this operation is the program counter. By calculation or subtracting to the PC a constant equal to the distance between the current didactics (ie, the instruction that is computing the address) and the desired location, we tin generate the desired accost without performing a load. The ARM programming organization provides an ADR pseudo-functioning to simplify this pace. Thus, as shown in Fig. 2.15, if we give location 0x100 the name FOO, we tin can use the pseudo-operation

Effigy 2.15. Calculating an absolute accost using the PC.

      ADR r1,FOO

to perform the same role of loading r1 with the address 0x100. Another technique is used in high-level languages such every bit C. As we will see when we discuss procedure calls, languages use a machinery called a frame to pass parameters between functions. For the moment, a simplified view of the procedure is sufficient. A annals holds a frame pointer (fp) that points to the acme of the frame; elements within the frame are accessed using offsets from fp. The assembler syntax [fp,#-n] is used to take the nthursday location from fp.

Instance ii.two illustrates how to implement C assignments in ARM didactics.

Example 2.2 C Assignments in ARM Instructions

We volition use the assignments of Fig. two.8. The semicolon (;) begins a annotate after an instruction, which continues to the end of that line. The statement

      x = (a + b) - c;

can exist implemented by using r0 for a, r1 for b, r2 for c, and r3 for x. We too demand registers for indirect addressing. In this example, we volition reuse the same indirect addressing annals, r4, for each variable load. The code must load the values of a, b, and c into these registers before performing the arithmetics, and information technology must store the value of x back to retentiveness when it is done.

Hither is the code generated by the gcc compiler for this statement. It uses a frame pointer to concord the variables: a is at −24, b at −28, c at −32, and x at −36:

      ldr r2, [fp, #-24]

      ldr r3, [fp, #-28]

      add r2, r2, r3

      ldr r3, [fp, #-32]

      rsb r3, r3, r2

      str r3, [fp, #-36]

The operation

      y = a∗(b + c);

can be coded similarly, only in this case nosotros will reuse more registers past using r0 for both a and b, r1 for c, and r2 for y. Once again, we will utilise r4 to store addresses for indirect addressing. The resulting code from gcc looks like this:

      ldr r2, [fp, #-28]

      ldr r3, [fp, #-32]

      add r2, r2, r3

      ldr r3, [fp, #-24]

      mul r3, r2, r3

      str r3, [fp, #-xl]

The C statement

      z = (a << ii) | (b & 15);

results in this gcc-generated code:

      ldr r3, [fp, #-24]

      mov r2, r3, asl #2

      ldr r3, [fp, #-28]

      and r3, r3, #15

      orr r3, r2, r3

      str r3, [fp, #-44]

More addressing modes

Nosotros have already seen 3 addressing modes: register, firsthand, and indirect. The ARM also supports several forms of base-plus-start addressing, which is related to indirect addressing. Merely rather than using a annals value straight as an address, the annals value is added to another value to class the address. For instance,

      LDR r0,[r1,#16]

loads r0 with the value stored at location r1   +   16. Here, r1 is referred to every bit the base and the immediate value the offset. When the offset is an firsthand, it may take whatever value up to 4096; another register may also exist used as the offset. This addressing style has two other variations: autoindexing and postindexing. Autoindexing updates the base register, such that

      LDR r0,[r1,#16]!

first adds sixteen to the value of r1 and then uses that new value equally the accost. The ! operator causes the base register to exist updated with the computed address so that it tin can be used again later. Our examples of base-plus-kickoff and autoindexing instructions will fetch from the same memory location, but autoindexing will too modify the value of the base register r1. Postindexing does not perform the get-go calculation until later on the fetch has been performed. Consequently,

      LDR r0,[r1],#16

will load r0 with the value stored at the retentivity location, whose address is given past r1, and and so add together 16 to r1 and set r1 to the new value. In this case, the postindexed style fetches a different value than the other 2 examples but ends upward with the same final value for r1 equally does autoindexing.

Nosotros have used the ADR pseudo-op to load addresses into registers to access variables because this leads to simple, easy-to-read lawmaking (at least by assembly language standards). Compilers tend to employ other techniques to generate addresses, because they must bargain with global variables and automated variables.

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